In a hierarchical cache system a block invalidate operation may be needed to invalidate a block of lines cached in the memory system. In the block coherence operation the user programs the base address and the number of words that need to be removed from the cache. The cache controller then iterates through the entire cache memory, and if it finds an address that is within the intended address range the controller will mark that particular set and way invalid. Block invalidate operations are typically required to keep data coherent within a multi processor system.
An example is illustrated in FIG. 6. In a multi core environment CPU1 601 is updating data within address range A. After CPU1 is done, an other CPU may start a process 603 and update data within the same address range. If during this time CPU1 needs to access data within this address range, it will need to get an updated copy of the data from the other CPU, however some of the required data still may be cached in CPU1—hence CPU1 will get old data unless a block invalidate 602 operation will be performed on CPU1's cache within the same address range A. This will then ensure that CPU1 request will result in a cache miss, and the correct data will be supplied from main memory.